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WPILib 2012
WPILibRoboticsLibraryforFRC
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WPILib 2012
WPILibRoboticsLibraryforFRC
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| create(tRioStatusCode *status) (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [static] |
| getSystemInterface()=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| kNumSystems enum value (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| readAvailableToLoad(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_MISO_Channel(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_MISO_Module(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_MOSI_Channel(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_MOSI_Module(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_SCLK_Channel(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_SCLK_Module(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_SS_Channel(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readChannels_SS_Module(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_BusBitWidth(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_ClockHalfPeriodDelay(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_ClockPolarity(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_DataOnFalling(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_FramePolarity(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_LatchFirst(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_LatchLast(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_MSBfirst(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readConfig_WriteOnly(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readDataToLoad(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readReceivedData(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readReceivedElements(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readStatus(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readStatus_Idle(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| readStatus_ReceivedDataOverflow(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| strobeClearReceivedData(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| strobeLoad(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| strobeReadReceivedData(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| strobeReset(tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| tAvailableToLoad_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tChannels_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tClearReceivedData_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tConfig_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tDataToLoad_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tIfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tLoad_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tReadReceivedData_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tReceivedData_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tReceivedElements_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tReset_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| tSPI() (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [inline] |
| tStatus_IfaceConstants enum name (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | |
| writeChannels(tChannels value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_MISO_Channel(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_MISO_Module(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_MOSI_Channel(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_MOSI_Module(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_SCLK_Channel(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_SCLK_Module(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_SS_Channel(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeChannels_SS_Module(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig(tConfig value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_BusBitWidth(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_ClockHalfPeriodDelay(unsigned char value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_ClockPolarity(bool value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_DataOnFalling(bool value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_FramePolarity(bool value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_LatchFirst(bool value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_LatchLast(bool value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_MSBfirst(bool value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeConfig_WriteOnly(bool value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| writeDataToLoad(unsigned int value, tRioStatusCode *status)=0 (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [pure virtual] |
| ~tSPI() (defined in nFPGA::nFRC_2012_1_6_4::tSPI) | nFPGA::nFRC_2012_1_6_4::tSPI | [inline, virtual] |
1.7.4
